Switching power supply device and a semiconductor integrated circuit

ABSTRACT

A capacitor is disposed between the output side and the ground potential of an inductor which creates an output voltage. A first switch element supplies a current from an input voltage to an input side of the inductor, and a second switch element which is turned on when the first switch element is off sets the input side of the inductor to a prescribed potential. A control circuit detects the arrival of the voltage on the input side of the inductor at a high voltage corresponding to the input voltage when the load circuit is in a light load state and the second switch element is off, and turns on the first switch element. It invalidates the detection output of the voltage detecting circuit when the load circuit is in a heavy load state and, after the second switch element is turned off, turns on the first switch element.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation of U.S. Ser. No. 11/979,093, filed Oct. 31, 2007,which is a continuation application of U.S. Ser. No. 11/510,819, filedAug. 28, 2006 (now U.S. Pat. No. 7,307,406).

The present application claims priority from Japanese patent applicationNo. 2005-248317 filed on Aug. 29, 2005 the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a switching power supply device and asemiconductor integrated circuit, more particularly to, for instance, atechnique that can be effectively applied to a switching power supplydevice for converting a high voltage into a low voltage.

Examples of transformer type synchronous rectifying converter includewhat are disclosed in the Japanese Unexamined Patent Publications Nos.2001-346380 and 2001-008444.

[Patent Reference 1] Japanese Unexamined Patent Publication No.2001-346380

[Patent Reference 2] Japanese Unexamined Patent Publication No.2001-008444

SUMMARY OF THE INVENTION

Switching power supply devices are required to be inexpensive, compactand efficient, operate on a low voltage and provide a large current. Forthis reason, they often use as switch elements N-channel type powerMOSFETS (hereinafter abbreviated to NMOSs), which are inexpensive, lowin on-resistance (low Ron) and in the quantity of gate charge (low Qgd).FIG. 7 shows a block diagram of a voltage step-down type switching powersupply device studied before the invention of the present application.The switching power supply device shown in FIG. 7 supplies a current tothe input side of an inductor L1 via a high potential side switch MOSFETQ1 which is subjected to switch control with a pulse width modulation(PWM) signal and, provided with an output capacitor Co between theoutput side of the inductor L1 and the ground potential of the circuit,obtains an output voltage Vout. Between the inductor L1 and the groundpotential, a low potential side switch MOSFET Q2 is provided. ThisMOSFET Q2 causes the input side of the inductor L1 when the MOSFET Q1 isturned off to be voltage-clamped to the ground potential of the circuit.The MOSFETs Q1 and Q2 are alternately, and their midpoint voltage Vswmanifests a waveform reciprocating between 0 V and an input voltage Vin.Stabilization of the output voltage Vout is achieved by adjusting theduty of PWM. More specifically, a PWM controller (not shown) is used togenerate a PWM signal matching the output voltage Vout, and that signalis given to a driver DVIC.

A continuous current mode (under heavy load) and a reverse current mode(under light load) in the voltage step-down type switching power supplydevice will be described. FIG. 8 shows the switching waveform in thecontinuous current mode and FIG. 9 shows the switching waveform in thereverse current mode. In the case of the continuous current mode shownin FIG. 8, a current IL flowing to the inductor (choke coil) L1 alwaysconstitutes a triangular wave of a positive value in at least one PWMcycle (a PWM signal is used in this case, though it need not be a PWMsignal but any signal that controls the output voltage Vout bycontrolling the switching of power MOSFETs, such as a pulse frequencymodulation (PFM) signal or a pulse density modulation (PDM) signal canbe used), and its average is equal to the output current Iout. When theoutput current Iout becomes smaller, the current IL drops on the whole.And it is seen that there are periods of negative values (in the reversedirection to the current I2 in the same graph as indicated by solidblack parts in FIG. 9. These are periods when a current is flowing inthe reverse direction from the output capacitor Co to the MOSFET Q2 viathe inductor L1.

From the turn-off of the high potential side MOSFET TQ1 until that ofthe low potential side MOSFET Q2 and from the turn-off of the MOSFET Q2until that of the MOSFET Q1, periods in which both are turned off areset to prevent a through current from flowing by the simultaneousturning-on of both MOSFETS. Such a period is generally known as a deadtime. Since both MOSFETs Q1 and Q2 are off during this dead time, theoutput current Iout during the period flows to the load side via thebody diode (parasitic diode between the source and the substrate) of theMOSFET Q2. As the equivalent resistance of the body diode is higher thanthe on-resistance of the MOSFET Q2, usually the dead time is designed tobe as short as practicable with a view to higher circuit efficiency, andits length is constant whether in the continuous current mode or in thereverse current mode. The inventors of the present application intend toimprove efficiency by a contrivance oriented to this reverse currentmode.

An object of the present invention is to provide a switching powersupply device and a semiconductor integrated circuit realizing suchefficiency improvement. This and other objects and novel features of theinvention will become apparent from the description in thisspecification when taken in conjunction with the accompanying drawings.

A typical one of the aspects of the invention disclosed in thisapplication will be briefly summarized below. A capacitor is disposedbetween the output side and the ground potential of an inductor whichcreates an output voltage. A first switch element supplies a currentfrom an input voltage to the input side of the inductor, and a secondswitch element which comes on when the first switch element is off setsthe input side of the inductor to a prescribed potential A controlcircuit detects the arrival of the voltage on the input side of theinductor at a high voltage corresponding to the input voltage when aload circuit is in a light load state and the second switch element isturned off, and turns on the first switch element. When the load circuitis in a heavy load state, it invalidates the detection output of thevoltage detecting circuit and, after the second switch element is turnedoff, turns on the first switch element.

The reverse current in a light load state can be utilized for chargingthe parasitic capacitance on the input side of the inductor, and theturn-on loss at the first switch element can be substantially reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram showing a switching power supplydevice, which is a preferred embodiment of the present invention.

FIG. 2 shows switching waveforms in the switching power supply device ofFIG. 1 when in the reverse current mode.

FIG. 3 illustrates loss analysis in switching power supply devicesaccording to the related art and the present invention under light load.

FIG. 4 illustrates circuit efficiency in the switching power supplydevices according to the related art and the invention.

FIG. 5 is a circuit diagram showing a switching power supply device,which is another preferred embodiment of the invention.

FIG. 6 is a schematic overall circuit diagram showing a switching powersupply device, which is still another preferred embodiment of theinvention.

FIG. 7 is a block diagram of a step-down type switching power supplydevice studied prior to the invention of the present application.

FIG. 8 shows switching waveforms in the switching power supply device ofFIG. 7 when in the continuous current mode.

FIG. 9 shows switching waveforms in the switching power supply device ofFIG. 7 when in the reverse current mode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a schematic circuit diagram showing a switching power supplydevice, which is a preferred embodiment of the present invention. Thisembodiment is intended for a so-called step-down type switching powersupply device which forms an output voltage Vout, stepped down from aninput voltage Vin. The input voltage Vin is supposed to be a relativelyhigh voltage, such as about 12 V, and the output voltage Vout, arelatively low voltage, such as about 1.3 V, though not particularlylimited to these voltages.

For the input voltage Vin, a current 11 is supplied from the input sideof an inductor L1 via a high potential side switch MOSFET Q1. Acapacitor Co is disposed between the output side of the inductor L1 andthe ground potential GND and the circuit, and the output voltage Voutsmoothed by this capacitor Co is formed. This output voltage Vout servesas the operational voltage for a load circuit, such as a microprocessorof a CPU. A switch MOSFET Q2 is provided between the input side of theinductor L1 and the ground potential GND of the circuit. This MOSFET Q2comes on when the switch MOSFET Q1 is off, brings the midpoint voltageVsw to the ground potential of the circuit and clamps the counterelectromotive voltage generated in the inductor L1. The switch MOSFETsQ1 and Q2 are composed of N-channel type power MOSFETs. As stated above,the connection point of the switch MOSFETs Q1 and Q2 is connected to theinput side of the inductor L1.

Though not illustrated in FIG. 1, a PWM signal which is formed by a PWMgenerating circuit and controls the output voltage Vout to about 1.3V isentered into an input control circuit CONT. The input control circuitCONT forms a high voltage signal HC and a low potential side signal LCmatching the PWM signal. Dead times are set for the two signals HC andLC. The high potential side signal HC is conveyed to a gate circuit G1through a level shift (level converting) circuit LS and to the gate ofthe high potential side switch MOSFET Q1 through a driver DV1. The lowpotential side signal LC is conveyed to the gate of the high potentialside switch MOSFET Q2 through a driver DV2.

In this embodiment, a low Ron and low Qgd N-channel type power MOSFET Q1is used as the high potential side switch element, which is operated asa source follower output circuit. For this reason, a booster circuit isprovided to obtain a high enough voltage as the midpoint potential tomatch the input voltage Vin, or in other words to prevent the midpointpotential Vsw from falling as much as the threshold voltage of theMOSFET Q1 and there inviting a loss.

The booster circuit so operates as to boost the gate voltage to a levelhigher than the input voltage Vin by more than the threshold voltage ofthe MOSFET Q1 when it is on. Thus, the midpoint is connected to one endof a boot strap capacitance CB. The other end of this boot strapcapacitance CB is connected to a power supply terminal Vcc via a diodeD1. The power voltage supplied from the power supply terminal Vcc is alow voltage, such as about 5 V, and is used as the operational voltagefor the input control circuit CONT, the low potential side circuit ofthe level shifter LS, the driver DV2 and a logic circuit LOG to bedescribed afterwards. When the MOSFET Q1 is off and the MOSFET Q2 is on,the boot strap capacitance CB is charged up from the power supplyterminal Vcc. When the MOSFET Q2 is turned off and the MOSFET Q1 isturned on, the gate voltage is boosted above the source side potentialby the charged-up voltage for the boot strap capacitance CB.

This embodiment is provided with voltage dividing resistances R1 and R2for dividing the input voltage. The resistance ratio between thesevoltage dividing resistances R1 and R2 is set to 1:4 or the like, thoughthe ratio is not limited to this, and forms a divided voltagecorresponding to 80% of the power voltage Vin. A voltage comparatorcircuit CMP compares the divided voltage and the midpoint voltage Vsw.When the midpoint voltage Vsw becomes higher than the divided voltage,the voltage comparator circuit CMP creates a detection signal and sendsit to the logic circuit LOG. The logic circuit LOG, receiving a lightload/heavy load mode signal MOD from a load circuit, controls thevalidity/invalidity of the detection signal of the voltage comparatorcircuit CMP, though its function is not limited to this. Thus, when thelight load mode is indicated, the detection signal of the voltagecomparator circuit CMP is validated. When the heavy load mode isindicated, the detection signal of the voltage comparator circuit CMP isinvalidated.

In this embodiment, the input control circuit CONT, the level shiftcircuit LS, the gate circuit G1, the logic circuit LOG, the drivers DV1and DV2, the voltage comparator circuit CMP and the voltage dividingresistances R1 and R2 are formed over a single semiconductor substrateto serve as a control circuit DVIC. Therefore, a terminal T1 to whichthe boot strap capacitance CB is connected, a terminal T2 to which theinput voltage Vin is inputted, a terminal T3 to which the gate of theMOSFET Q1 is connected, a terminal T4 to which the gate of the MOSFET Q2is connected, a terminal T5 to which the light load/heavy load modesignal MOD is inputted, a terminal T6 to which the PWM signal isinputted and a terminal T7 to which the power voltage Vcc is suppliedare provided as external terminals.

Incidentally, a single semiconductor integrated circuit may as well beconfigured of the MOSFET Q1 formed over a first semiconductor substrate,the MOSFET Q2 formed over a second semiconductor substrate, the controlcircuit DVIC formed over a third semiconductor substrate, the controlcircuit DVIC, the MOSFET Q1 and the MOSFET Q2 being encapsulated in asingle package. Alternatively, a single semiconductor integrated circuitmay be configured of the control circuit DVIC and the MOSFET Q1 togetherformed over the first semiconductor substrate and the MOSFET Q2 formedover the second semiconductor substrate, the control circuit DVIC, theMOSFET Q1 and the MOSFET Q2 being encapsulated in a single package.

FIG. 2 shows switching waveforms when in the reverse current mode, inwhich in the switching power supply device according to the invention isunder light load. The switching between the turning-off of the lowpotential side MOSFET Q2 and the turning-on of the high potential sideMOSFET Q1 involve, as shown in the expanded part of FIG. 2, when the lowpotential side MOSFET Q2 is turned off, there are periods of negativevalues as indicated by solid black parts as in the foregoing. If thehigh potential side MOSFET Q1 is kept off then, the negative currents−12 will enable the parasitic capacitance between the midpoint theground potential of the circuit to be utilized for charging and therebyto let the midpoint potential Vsw rise.

In the embodiment of FIG. 1, as the arrival of this midpoint potentialVsw at about 80% of the input voltage is detected by the voltagecomparator circuit CMP and the high potential side MOSFET Q1 is turnedon through the logic circuit LOG-gate circuit G1 and the driver DV1, theMOSFET Q1 is turned on at a timing when the midpoint potential Vsw hasbecome substantially equal to the input voltage Vin with the delay timeon the signal path being taken into account. This makes it possible toreduce the power needed to let the midpoint voltage Vsw rise to theinput voltage Vin to zero. In other words, the turn-on loss required tolet the midpoint voltage Vsw from 0 V to the input voltage Vin when theMOSFET Q1 is turned on can be represented by Equation (1) below.

Turn-on loss=½×Cx×Vin² ×f (where Cx is the parasitic capacitance betweenthe midpoint and the ground potential GND of the circuit and f is theswitching frequency)

As stated above, when in the reverse current mode, there are periodsduring which the current flows back from the output capacitor Co to thelow potential side MOSFET Q2, and when the low potential side MOSFET Q2is turned off, that current charges parasitic capacitance between thedrain and source of the low potential side MOSFET (between the midpointand the ground potential GND of the circuit). In this embodiment, themidpoint voltage Vsw after the low potential side MOSFET Q2 is turned ofwhen in the reverse current mode is monitored by the voltage comparatorcircuit CMP, and when the midpoint voltage Vsw has substantially reachedthe input voltage Vin (for instance, a potential of 80% of Vi), the highpotential side MOSFET Q1 is turned on.

Depending on the level of the reverse current, the midpoint voltage Vswmay not reach the input voltage Vin. In such a case, as the voltagecomparator circuit CMP forms no detection signal, a maximum limit isimposed on the length of the dead time between the turning-off of thelow potential side MOSFET Q2 until the turning-on off of the highpotential side MOSFET Q1. In the embodiment of FIG. 1, the maximum deadtime≦about 50 ns is provided in the logic circuit LOG (permissible timesetting circuit), and after the lapse of this time the high potentialside MOSFET Q1 is turned on by way of the gate circuit G1-driver DV1.

FIG. 3 illustrates loss analysis in switching power supply devicesaccording to the related art and the present invention under light load.The circuit conditions are supposed to be the input voltage Vin=12 V,the output voltage Vout=1.3 V, the output current Iout=1.0 A, thefrequency f=500 KHz and the inductor L1=0.45H. There are eight types oflosses including (1) Q1 turn-off loss, (2) Q1 turn-on loss, (3) bodydiode loss, (4) Q2 conduction loss, (5) Q1 conduction loss, (6) 02 driveloss, (7) Q1 drive loss, (8) driver I C loss. Of these, (2) the Q1turn-on loss is as stated above, and other losses can be represented asfollows.

Turn-off loss=0.5×Vin×(Iout+0.5×Ipp)² ×Ins/A×f  (1)

Body diode loss=TD/TS×VF×(Iout+0.5×Ipp) (where TD is the dead time, TSis the cycle and VF is the voltage of the body diode in the forwarddirection)  (3)

Conduction loss=(Iout×Duty×√(1+⅓(0.5×Ipp/Iout))²)² ×Ron (where Ipp isthe ripple current of IL, and Ron is the on-resistance of MOSFET)  (4),(5)

Drive loss=Qg×Vg×f (where Qg is the gate charge of MOSFET and Vg is thegate drive voltage)  (6), (7)

Driver loss=Icc×Vcc (where Icc is the self-consumed current and Vcc isthe power voltage)  (8)

According to the invention of the present application, (2) the Q1turn-on loss, which accounts for about 40% of the total losses, can beeliminated.

FIG. 4 illustrates circuit efficiency in the switching power supplydevices according to the related art and the invention. This graph showsthe circuit efficiency for the output current Iout. Since it is possibleto eliminate the turn-on loss of Q1 under light load and set the deadtime to the minimum under heavy load as stated above, the overallcircuit efficiency can also be enhanced, by as much as approximately 8%when the output current Iout is 1 A. In other words, the output currentIout is small, efficiency can be enhanced by eliminating theaforementioned (2) turn-on loss of Q1.

FIG. 5 is a circuit diagram showing a switching power supply device,which is another preferred embodiment of the invention. In thisembodiment, the input control circuit CONT and the logic circuit LOG ofFIG. 1 above are shown more specifically. Herein, the booster circuitcomprising the boot strap capacitance CB and other elements is notshown. The PWM signal is supplied to one input each of an AND gatecircuit G2 and a NOR gate circuit G3. The output signal of the driverDV2 driving the low potential side MOSFET Q2 is inverted and inputted tothe other input of the AND gate circuit G2. The output signal of thedriver DV1 driving the high potential side MOSFET Q1 is inputted to theother input of the NOR gate circuit G3. The output signal HC of the ANDgate circuit G2 is conveyed to the input of the driver DV1 through thelevel shift circuit LS and an AND gate circuit G4. Further, the outputsignal LC of the NOR gate circuit G3 is conveyed to the input of thedriver DV2.

This basically causes the MOSFET Q1, when the PWM signal is at a highlevel, to be turned on when the output signal of the driver DV2 whichturns off the MOSFET Q2 is at a low level and the MOSFET Q2, when thePWM signal is at a low level, to be turned on when the output signal ofthe driver DV1 which turns off the MOSFET Q1 is at a low level. In thisway, the basic dead time is set to a short period of monitoring thelevels of the drivers D1 and DV2.

In this embodiment, the detection signal of the voltage comparatorcircuit CMP is supplied to one input of a NOR gate circuit G5. Theoutput signal of a delay circuit DLY which delays the output signal ofan inverter circuit IV1 which inverts the output signal of the driverDV2 is supplied to the other input of the NOR gate circuit G5. The delaycircuit DLY, constituting the permissible time setting circuit, limitsthe maximum dead time under light load. The output signal of the NORgate circuit G5 is supplied to one input of a NAND gate circuit G6. Amode signal MOD which is raised to a high level (logic 1) when under thelight load is supplied to the other input of the NAND gate circuit G6.The output signal of this NAND gate circuit G6 is used as a controlsignal for the AND gate circuit G4 which conveys the drive signal forthe high potential side MOSFET Q1.

When the detection signal of the voltage comparator circuit CMP and theinput signal from the delay circuit DLY are at a low level (logic 0),the NOR gate circuit G5 is outputting a high level (logic 1). Therefore,when the mode signal MOD is at a high level (logic 1), the NAND gatecircuit G6 creates a low level output signal. Therefore, even when thePWM signal is at a high level and moreover the output signal of thedriver DV2 which turns off the MOSFET Q2 is at a low level as describedabove, the turning-on of the MOSFET Q1 is stopped. When the detectionsignal of the voltage comparator circuit CMP varies to a high level,namely the midpoint voltage Vsw reaches about 80% or more of the inputvoltage Vin, the output signal of the NOR gate circuit G5 varies to alow level. Accordingly, as the NAND gate circuit G6 creates an outputsignal of a high level to open the gate of the AND gate circuit G4, thehigh potential side MOSFET Q1 is turned on through the driver DV1.

If the detection signal the voltage comparator circuit CMP remains at alow level even after the lapse of the delay time of the delay circuitDLY, namely if the reverse current is too small to charge the parasiticcapacitance sufficiently, the output signal of the delay circuit DLYwill vary to a high level and causes the output signal of the NOR gatecircuit G5 to vary to a low level as described above. Therefore, as theNAND gate circuit G6 creates an output signal of a high level to openthe gate of the AND gate circuit G4, the high potential side MOSFET Q1is turned on through the driver DV1.

When the load of the load circuit (CPU or the like) is heavy, the modesignal MOD is brought down to a low level (logic 0). This causes theNAND gate circuit G6 to output a high level irrespective of the outputsignals of the voltage comparator circuit CMP and the delay circuit DLY.Therefore, the high potential side MOSFET Q1 is cause to create acontrol signal HC which achieves turning-on at the timing of the lowlevel of the output signal of the driver DV2 of the low potential sideMOSFET Q2. This is intended to reduce losses in the body diode andthereby improve circuit efficiency under heavy load.

FIG. 6 is a schematic overall circuit diagram showing a switching powersupply device, which is still another preferred embodiment of theinvention. For this embodiment, the input voltage Vin is supposed to bea relatively high voltage, such as about 12 V and the output voltageVout, a relatively low voltage, such as about 0.8 V, though the choiceis not particularly limited to these. This output voltage Vout is usedas the operational voltage for load circuits such as FPGA and CPU.

This embodiment is composed of the control circuit DVIC mounted with theinput control circuit CONT, the level shift circuit LS and the driversDV1 and DV2, shown as a typical example in FIG. 1 and FIG. 5 above,together with a PWMIC for creating the PWM signal and unit componentsincluding the switch MOSFETs Q1 and Q2, the inductor L1, the outputcapacitor Co and so forth. In order to control the output voltage Voutto a relatively low voltage, such as about 0.8 V, though notparticularly limited to this, there is provided a voltage amplifiercircuit comprising an operational amplifier OPA and resistances R3 andR4. This voltage amplifier circuit constitutes a feedback control unit,which creates a voltage-amplified output voltage Vout′, such as theoutput voltage Vout×(R3+R4)/R4. This voltage Vout′ is divided bydividing resistances R5 and R6 in a ratio of R6/(R5+R6), and the dividedvoltage is conveyed to a feedback terminal FB of the PWM control circuitPWMIC.

The feedback voltage conveyed to the feedback terminal FB is supplied toone input (−) of an error amplifier EA of the PWMIC. A band gapreference voltage Vref of about 1 V, though not particularly limited tothis level, is supplied to the other input (+) of the error amplifierEA. The differential voltage between the feedback voltage and thereference voltage Vref is supplied to one input (−) of a voltagecomparator circuit VC. A triangular wave created by a triangular wavegenerating circuit is supplied to the other input (+) of the voltagecomparator circuit VC. The output signal of the voltage comparatorcircuit VC is inputted as a PWM signal to the input control circuit CONTprovided in the driver DVIC. It is not particularly limited to a PWMsignal, but what controls the output voltage Vout by regulating theswitching of power MOSFETs, such as a pulse frequency modulation (PFM)signal or a pulse density modulation (PDM) signal, can be used as well.

Where a higher voltage than the band gap reference voltage Vref of about1 V or so, such as 1.3 V, provided in the PWMIC is to be formed, as theoutput voltage Vout, the aforementioned voltage amplifier circuitcomprising an operational amplifier OPA and resistances R3 and R4 can bedispensed with. By selectively disposing such voltage amplifier circuitcomprising an operational amplifier OPA and resistances R3 and R4, theoutput voltage Vout can be set in a broad range with the combination ofcircuits comprising DVIC, PWMIC and external components.

Although the invention accomplished by the present inventors have beenhitherto described in specific terms with reference to preferredembodiments thereof, the invention is not limited to these embodiments,but can be modified in various manners without deviating from itsessentials. For instance, the logic circuit LOG to validate/invalidatethe detection signal of the voltage comparator circuit CMP can berealized in one or another of a number of specific configurations. Or,the mode signal MOD may be one using a signal such as a sleep mode or astandby mode of the load circuit CPU, or alternatively the switchingpower supply device itself may be provided with a circuit for detectinga light load state. This invention can be expensively used for voltagestep-down type switching power supply devices.

1. A switching power supply device, comprising: an inductor, a capacitorcoupled between an output side of said inductor and a ground potential,a first switch element for supplying a current from an input voltage toan input side of said inductor, a second switch element which comes onwhen said first switch element is off to set the input side of saidinductor to a predetermined potential, and a control circuit whichgenerates a first control signal to be supplied to said first switchelement and a second control signal to be supplied to said second switchelement so as to set the output voltage obtained from the output side ofsaid inductor to a desired voltage, wherein said control circuit:includes a voltage detecting circuit which generates a detection signalby which a reach of the voltage on said input side of said inductor to afirst voltage is detected, controls said first switching element to turnon with the detection signal of said voltage detecting circuit when aload circuit supplied with said output voltage is in a first load stateafter said second switch element is turned off, and controls said firstswitching element to turn on without the detection signal of saidvoltage detecting circuit when said load circuit is in a second loadstate after said second switch element is turned off.
 2. The switchingpower supply device according to claim 1, wherein said control circuitcomprises a permissible time setting circuit and, in case the detectionsignal of said voltage detecting circuit is not generated within a setperiod of said permissible time setting circuit, controls to turn onsaid first switch element.
 3. The switching power supply deviceaccording to claim 2, wherein the first load state of said load circuitcorresponds to a state when an operating mode of said load circuit is astandby or sleep mode.
 4. The switching power supply device according toclaim 3, wherein said control circuit comprises a voltage dividingcircuit for generating a divided voltage as said first voltage, andwherein said voltage detecting circuit performs said detecting operationwith said divided voltage as a reference voltage.
 5. The switching powersupply device according to claim 4, wherein said first switch elementand said second switch element are N-channel MOSFETs, and wherein theswitching power supply device further comprises: a booster circuitincluding a boot strap capacitance having one end which is connected tothe source of the N-channel MOSFET constituting said first switchelement, and a level shift circuit for generating a drive signal using aboosted voltage generated by said booster circuit, and the drive signalis coupled to a gate of the N-channel MOSFET constituting said firstswitch element.
 6. The switching power supply device according to claim5, wherein the control circuit including said voltage detecting circuitand voltage dividing circuit is formed on a single semiconductorintegrated circuit, and wherein said first and second switch elements,inductor, capacitor and boot strap capacitance constituting the boostercircuit are composed of externally attached components.
 7. The switchingpower supply device according to claim 6, further comprising a PWMsignal generating circuit for generating a PWM signal which causes saidoutput voltage correspond to a predetermined reference voltage, whereinsaid PWM signal is inputted to said control circuit to set an on-periodof said first switch element.
 8. A switching power supply devicecomprising: an inductor, a capacitor coupled between an output side ofsaid inductor and a ground potential, a first switch element forsupplying a current from an input voltage to an input side of saidinductor, a second switch element which comes on when said first switchelement is off to set the input side of said inductor to a predeterminedpotential, and a control circuit which controls said first and secondswitch elements so as to set an output voltage obtained from the outputside of said inductor to a predetermined voltage, said switching powersupply comprising: a first state having a period in which a currentflows from a load circuit to which said output voltage is supplied to asecond switch element in at least one PWM cycle, a second state in whicha current continuously flows from said switching power supply device tosaid load circuit, wherein said control circuit: includes a voltagedetecting circuit which generates a detection signal by which a reach ofthe voltage on said input side of said inductor to a first voltage isdetected, controls to turn on said first switch element in said firststate with the detection signal of said voltage detecting circuit whensaid second switch element is turned off, controls turn on said firstswitch element in said second state after said second switch element isturned off.
 9. The switching power supply device according to claim 8,wherein said control circuit comprises a permissible time settingcircuit for use in said first state and generates a second controlsignal which, in case the detection signal of said voltage detectingcircuit is not generated within a set period of said permissible timesetting circuit, turns on said first switch element after the setperiod.
 10. The switching power supply device according to claim 9,wherein the first state corresponds to a state when an operating mode ofsaid load circuit is a standby or sleep mode.
 11. The switching powersupply device according to claim 10, wherein said control circuitcomprises a voltage dividing circuit for generating a divided voltage assaid first voltage which is lower than said input voltage, and whereinsaid voltage detecting circuit performs said detecting operation withsaid first voltage as a reference voltage.
 12. The switching powersupply device according to claim 11, wherein said first switch elementand second switch element are N-channel MOSFETs, the switching powersupply device further comprises: a booster circuit including a bootstrap capacitance of which one end is connected to the source of theN-channel MOSFET constituting said first switch element, and a levelshift circuit for generating a drive signal using a boosted voltagegenerated by said booster circuit, the drive signal being coupled to agate of the N-channel MOSFET constituting said first switch element. 13.A semiconductor integrated circuit comprising: a first switch elementwhich supplies a current from an input voltage to a external loadcircuit via an external inductor, a second switch element which comes onwhen said first switch element is off and supplies a current to saidload circuit via said inductor, and a control circuit which generates acontrol signal to be supplied to said first and second switch elementsso as to set the voltage obtained to be supplied to said load circuit toa desired level, wherein said control circuit: includes a voltagedetecting circuit which generates a detection signal by which the reachof the voltage on the input side of an inductor at a first voltage isdetected, validates the operation of said voltage detecting circuit whensaid load circuit is in a first state, and generates the control signalwhich turns on the first switch element using the detection signal ofsaid voltage detecting circuit, and invalidates the detection signal ofsaid voltage detecting circuit when said load circuit is in a secondstate and, turns on said first switch element.
 14. The semiconductorintegrated circuit according to claim 13, wherein the first load stateof said load circuit corresponds to a state when an operating mode ofsaid load circuit is a standby or sleep mode.
 15. The semiconductorintegrated circuit according to claim 13, wherein said control circuitcomprises a voltage dividing circuit for generating a divided voltagelower than said input voltage, and wherein said voltage detectingcircuit generates the detection signal with said divided voltage as areference voltage.
 16. The semiconductor integrated circuit according toclaim 13, wherein said first switch element and second switch elementare N-channel MOSFETS, the switching power supply device furthercomprises: a booster circuit generates a boosted voltage with a externalboot strap capacitance of which one end is connected to the source ofthe N-channel MOSFET constituting said first switch element, and a levelshift circuit for generating a drive signal using the boosted voltagegenerated by said booster circuit, the level shift circuit being coupledto a gate of the N-channel MOSFET constituting said first switchelement.
 17. The semiconductor integrated circuit according to claim 13,wherein said first switch element is formed over a first semiconductorsubstrate, wherein said second switch element is formed over a secondsemiconductor substrate, wherein said control circuit is formed over athird semiconductor substrate, and wherein said first, second and thirdsemiconductor substrates are molded in a single package.